1. Field
Embodiments described herein relate generally to static random access memory.
2. Description of Related Art
A static random access memory (SRAM) includes multiple memory cells, which consist of MOS (metal oxide semiconductor) transistors. Each transistor has a various characteristic due to the random dopant fluctuation (RDF). For this reason, there are some unreadable or unwritable cells in a large capacity SRAM. Therefore it is important to secure the read and write operations against the characteristic variation. Nevertheless, if transistors are shrinked to reduce the area of the chip, variation among the transistors becomes larger, and accordingly variation in characteristics among the memory cells becomes larger. On the other hand, if the power supply voltage of the SRAM is decreased to reduce the power consumption, some transistors, which have a higher threshold voltage, can operate under linear region. This can makes a mismatch among the current drivability of the memory-cell transistors and causes failure in read and write operations.
It has been known that the controlling of terminal voltages of the inverters constituting each SRAM memory cell is effective for coping with these kinds of problems. As one of technologies for controlling a terminal voltage of an inverter, there is disclosed a technology in which: a source terminal of a PMOS (p-type metal oxide semiconductor) transistor of the inverter is connected with a capacitor element constituted of a metal interconnection; and thereby the PMOS transistor and the capacitor element share charges to adjust the source voltage of the PMOS transistor (Digest of Technical Paper, 2006 Symposium on VLSI circuits, pp. 17-18). An advantage of this technology is that capacitor elements can be easily configured by use of metal interconnections running above the memory cell array. Therefore it doesn't require any additional chip area.